In recent years, silicon integrated circuits have been utilized for new and diverse applications, such as pressure transducers, thermal print heads and ink jet nozzle arrays. Another significant use of silicon integrated circuits is in the area of electrostatic charge-sensing applications. The latter application typically requires the retaining of a small air gap (nominally 10 micrometers) between the photoreceptor (film) surface and the charge-sensing array or active chip surface.
Two features of significant impact on device fabrication are the large die size and the requirement that bonding wires do not interfere with the small sensor-to-film air gap. The former generally necessitates use of an electron beam system for mask making. The latter constrains or prohibits the use of conventional die bonding in which bond wires, typically 25 micrometers in diameter, lead up from the die surface to attach to the package pads.
Consequently, the hitherto approach was the use of so-called backside contacts. Backside contacts typically are made by thermomigration of molten alloy zones through the thickness of the water. With this technique, pipes of heavily aluminum-doped silicon are formed which are junction-isolated from the N-type substrate. This technique requires relatively high process temperatures, for example, 1100 degrees celsius, which is generally incompatible with silicon wafer fabrication. For a more thorough discussion of thermomigration reference may be had to the article titled "Random walk of liquid droplets migrating in silicon" by T. R. Anthony and H. E. Cline published in the Journal of Applied Physics, Volume 45, No. June 1976.
The present applicant observed that the use of the prior art so-called backside contacts resulted in numerous deficiencies and disadvantages such as the difficulty of forming the via(s) or holes about the periphery of the chip, the use of relatively high temperatures to effect the holes and the thermomigration, and the necessity to use N-type substrates when aluminum thermomigration is effected on a silicon wafer or chip.
The use of such relatively high process temperatures is generally incompatible with normal silicon wafer fabrication and can result in damage to the chip and its integrated circuitry. The (P-N) junction isolation, formed at the silicon wafer via(s) with aluminum thermomigration, limits or constrains the polarity of the externally applied voltage that can be utilized.
Some prior references of interest include U.S. Pat. No. 3,904,442 issued to T. R. Anthony and H. E. Cline; U.S. Pat. No. 3,902,925 issued to T. R. Anthony and H. E. Cline; U.S. Pat. No. 2,813,048 issued to W. G. Pfann; and U.S. Pat. No. 3,898,106 issued to H. E. Cline and T. R. Anthony.
These references are mentioned as being representative of the prior art and other pertinent references may exist. None of the above cited references are deemed to affect the patentability of the present claimed invention.
The present invention involves a silicon chip and method of fabrication thereof so as to afford a solution to the difficulties, disadvantages and problems encountered with the prior art. For example, in contrast to the prior art, the present invention provides a semiconductor chip having a peripheral ledge formed below the active chip surface. The bond pads are, therefore, recessed, which enables the wire bonds to lie below the active chip surface. The formation of the ledge(s) and bond pads may be effected without the use of relatively high temperatures. The surface of the chip or wafer is passivated, i.e., oxide coated, to substantially prevent any electrical (leakage) current flow between the bond pads. In this manner the prior art via(s) P-N junctions are eliminated, which obviates the limitations on the polarity of the voltages that can be externally applied to the silicon chips fabricated in accordance with applicants's invention.